1. Field of the Invention
The present invention relates to a mobile communication system, and more particularly to a method and an apparatus for processing data at a high speed by a User Equipment (UE).
2. Description of the Related Art
In general, a commercial transmission data rate in a mobile communication system has a maximum data rate of about 100 Mbps, and modem chips of each UE in charge of data transmission/reception with a Node B have nearly the same structure and use nearly the same data processing scheme. Procedures for processing reception data and transmission data can be divided into hardware procedures and software procedures. Specifically, most procedures performed by physical layer entities, such as modulation/demodulation, interleaving/deinterleaving, and encoding/decoding, are processed by hardware, and protocol stacks, such as signaling and Automatic Repeat reQuest (ARQ), are processed by software.
FIG. 1 is a block diagram illustrating a structure of a conventional UE modem.
Referring to FIG. 1, in the case of downlink for receiving data from a Node B, data received through an antenna is input to a modem 131 within a modem chip 130 through a Radio Frequency (RF) filter 110 and a Broad Band Amplifier (BBA) 120. Then, the data is subjected to processing, such as demodulation and decoding, in the modem 131, and is then stored in an external memory 140. The Central Processing Unit (CPU) 132 either stores the data having been subjected to the protocol stack process in the external memory 140 within the UE according to the location of an Application Processor (AP) or transmits the data to an external device 170 through an external interface.
During an uplink for transmitting data to the Node B, data received from the external device 170 or the AP 151 within the UE is first stored in the external memory 140, is subjected to the protocol stack process in the CPU 132, and is then transferred to the modem 131. Thereafter, the data is subjected to procedures, such as encoding and modulation, and is then transmitted to the Node B through the BBA 120, the RF filter 110, and the antenna.
FIG. 2 is a signal flow diagram illustrating a process of processing data received by a receiver unit of a conventional 3rd Generation Partnership Project (3GPP)-based UE modem.
Referring to FIG. 2, data received through an antenna is input to a modem after passing through an RF filter. Then, the modem performs demodulation and decoding of the data, stores the data in a decoder buffer, and then generates a Reception (Rx) interrupt in step 201. Then, a Lower Medium Access Control (LMAC) device transfers the data from the decoder buffer to an external memory in step 202, and generates a data transfer done signal in step 203. The LMAC may be implemented either by hardware or by software to be processed by the CPU. When the data is completely transferred to the external memory, the CPU reads the data in the external memory and sequentially performs the protocol stack processes for protocols, such as Medium Access Control (MAC) protocol, Radio Link Control (RLC) protocol, a Radio Resource Control (RRC) protocol, and Packet Data Convergence Protocol (PDCP). When the protocol stack processes are completed, the CPU sends the data to the application layer. FIG. 2 illustrates transmission of data to a Personal Computer (PC) through a Universal Serial Bus (USB) device, based on an assumption that data is downloaded through a PC, which is one of representative high-speed data applications. That is, the CPU reads data from the external memory in step 207, and arranges the data and stores the arranged data again in the external memory in step 208. Thereafter, when an interrupt is received from the USB device in step 209, the CPU reads the data from the external memory and transfers the read data to the USB in step 210. In step 211, the CPU determines whether the data transfer has been completed. If the data transfer has been completed at step 211, the CPU deallocates the memory in step 212. If the data transfer has not been completed at step 211, the CPU returns to step 207.
When the application operates within the modem chip, the data may be transmitted either to a predetermined memory or to an external device through an external interface device, such as PC Memory Card International Association (PCMCIA) or Local Area Network (LAN).
FIG. 3 is a signal flow diagram illustrating a process of processing data by a transmitter unit of a conventional 3GPP-based UE modem.
Referring to FIG. 3, when data is received through an external interface device, such as a Universal Serial Bus (USB) device, in step 301, the CPU transfers the received data to the external memory in steps 302 and 303 and performs a PDCP process in step 304. In step 305, if an outgoing interrupt is received from an encoder buffer, the CPU determines a transport format by using allocated resources and various conditions. In steps 306 and 307, the CPU performs RLC and MAC processes, and then generates a MAC Protocol Data Unit (PDU). Then, the CPU reads data from the external memory in step 308, arranges the data in step 309, and then transfers the data to the encoder buffer in step 310.
In most cases, during the process of producing a MAC PDU from multiple RLC PDUs, a one-time data copy is performed for all the MAC PDUs, in order to achieve data alignment and concatenation.
The largest problems in applying the conventional UE structure and data processing scheme as described above to a high-speed data communication of at least 50 Mbps include the external memory access speed and the bottleneck phenomenon at the external memory interface. In the case of data transmission using an internal bus, it is possible to achieve a transmission of as much data as the bus bandwidth allows within 1˜2 cycles with reference to the internal bus clock cycle. For example, when the bus bandwidth is 32 bits, it is possible to a achieve transmission of 32 bits of data within 1˜2 cycles. However, in order to transmit data to the external memory or read data from the external memory, an average of 10˜15 cycles of access time is necessary. Although the length of the access time depends on various parameters, such as the type of the external memory, the type of the memory controller, the bus speed, and the types and the number of Internet Protocols (IPs), the access time to the external memory has a length of at least 10 cycles on the average, which corresponds to a maximum of at least ten times of that of the internal memory. In the case of CPU processing, it is possible to reduce the number of times the external memory is accessed by using a cache memory. However, in the case of data transmission, new data is transmitted or received at every time unit, and the data size is much larger than the size of the cache memory. Therefore, in the case of data transmission, it is nearly impossible to reduce the number of times the external memory is accessed, and a time required to write on the external memory or read from the external memory increases by a maximum of at least ten times.
FIG. 4 is a block diagram illustrating a simplified structure of an external memory interface of a conventional UE.
Referring to FIG. 4, each IP block, such as a CPU 410, a Direct Memory Access (DMA) block 420, a modem 430, and an external device InterFace (I/F) 440, can access an external memory 470 through a memory controller 450 performing the scheduling. An internal bus 460 has a multi-layer structure and can perform parallel processing. However, it is noted that a bottleneck phenomenon occurs in the memory controller 450. Further, an increase in the number of external memory interfaces requires an increase in the number of pins of the modem chip by the size of the bus bandwidth.
Another problematic point in the high-speed data communication is the performance of the CPU. The higher the data transmission rate, the greater the number of processes performed by the CPU. However, since the CPU has a limited Million Instructions Per Second (MIPS) rate, the CPU may cause a system error when it fails to properly perform each process within the required time.
For example, a chip supporting High Speed Downlink Packet Access (HSDPA) uses a CPU clock of about 300 MHz in order to process data at a speed of 7.2 Mbps. However, there is a technical limit in increasing the CPU clock in order to increase the processing capability or reduce the internal bus speed and the access time. Therefore, it is not easy to achieve high-speed data processing by improving hardware performance.